1. Field of the Invention
Example, non-limiting embodiments of the present invention relate generally to a semiconductor device and a method of manufacturing the same. More particularly, example, non-limiting embodiments of the present invention relate to a semiconductor device having an active pattern that extends from a semiconductor substrate and a method of manufacturing the same.
2. Description of the Related Art
A semiconductor device may be highly integrated so that an area of an active region may be reduced. Accordingly, a channel length of a metal-oxide semiconductor (MOS) transistor, for example, formed on the active region may also be reduced. When the channel length of the MOS transistor is reduced, source/drain regions may have an influence on an electric field and/or a voltage in a channel region. This phenomenon may be referred to as a short channel effect. In addition, a channel width may be reduced proportionally to the reduction of the active region so that a threshold voltage may be increased. This phenomenon may be referred to as a narrow channel effect or a narrow width effect.
A semiconductor device having both a reduced size and an improved capacity has been the subject of development. According to such development, the semiconductor may include a vertical transistor structure such as a fin structure, a fully depleted lean-channel transistor (DELTA) structure and a gate-all-around (GAA) structure.
For example, a fin type MOS transistor may include thin channel fins in parallel with each other. The thin channel fins may be positioned between source/drain regions. The fin typed MOS transistor may also include a gate electrode formed on both side faces of the channel fin. In the fin type MOS transistor, the gate electrode may be controlled by selectively providing a current to the side faces of the channel fin, thereby suppressing the short channel effect. However, the channel fins of the fin typed MOS transistor may be parallel to each other in a width direction of the gate electrode, and therefore a channel region and the source/drain regions may occupy a substantial area of the fin type MOS transistor. Also, the number of channels may be increased, and therefore a junction capacitance between the source/drain regions may be increased.
A MOS transistor having a DELTA structure may include an active layer that may include a vertically protruded portion that may serve as a channel layer. A gate electrode may enclose the protruded portion of the active layer. A height of the protruded portion of the active layer may correspond to a width of the channel layer. A width of the protruded portion of the active layer may correspond to a thickness of the channel layer. Both side faces of the protruded portion of the active layer may be available as channel layers, and therefore the channel may have an increased width, thereby preventing the narrow channel effect. In addition, when a width of the protruded portion is decreased, depletion layers of the channel layer that are formed on both of the side faces of the protruded portion may be overlapped so that the channel layer may have an increased electric conductivity.
However, in order to form the MOS transistor having the DELTA structure on a bulk silicon substrate, the bulk silicon substrate may be etched to form a vertical protrusion where the channel layer may be formed. The vertical protrusion may be covered with an oxidation-preventing layer. An oxidation process may be performed on the silicon substrate having the vertical protrusion. When the oxidation process is excessively performed, an interface between the protrusion and a portion of the silicon substrate that is not covered with the oxidation-preventing layer may be oxidized by lateral diffusion of oxygen, so that the vertical protrusion may be separated from the silicon substrate. When the vertical protrusion is separated from the substrate body, the channel layer may have a narrow width. Also, a single crystalline layer in the vertical protrusion may be damaged by stresses generated in the oxidation process.
The MOS transistor having the DELTA structure may be formed using a silicon-on-insulator (SOI) substrate. Here, an SOI layer may be etched to form a channel region having a narrow width. Thus, problems caused by the excessive oxidation of the bulk silicon substrate may be reduced. However, a width of the channel may be limited by a thickness of the SOI layer. For example, because a fully depleted type SOI substrate has a thickness of about 100 Å to 900 Å, a width of the channel may be limited.
A MOS transistor having a GAA structure may have an active region formed using an SOI layer. A gate electrode may enclose a channel region formed in an active region, which may be covered with a gate insulation layer. Thus, excessive oxidation of the bulk silicon substrate may be reduced.
However, in order to enclose the active pattern where the channel region is formed therein with a gate electrode, a buried oxidation layer positioned beneath the active pattern may be partially removed using an undercut effect of an isotropic etching process, for example. Here, since the SOI layer may be used for the channel region and source/drain regions, a lower portion of the source/drain regions as well as a lower portion of the channel region may be partially removed in the isotropic etching process. When a conductive layer such as the gate electrode is formed, the conductive layer may be formed on the lower portion of the source/drain regions as well as on the channel region. As a result, a parasitic capacitance may be increased.
In addition, a lower portion of the channel region may be horizontally etched in the isotropic etching process. A horizontal length and/or a width of a tunnel to be filled with the gate electrode may be increased. As a result, it may be difficult to manufacture a MOS transistor having a gate length that may be shorter than a channel length. In addition, there may be a limitation in reducing the gate length.